Nvidia's Next AI Rack Just Slipped to 2028. The Chip Works. The Circuit Board Doesn't.

TL;DR

Nvidia's next-generation AI rack, the Kyber NVL144, has slipped more than 12 months to 2028, according to a July 6 report from analyst firm SemiAnalysis that was picked up by CNBC. Jensen Huang demoed the thing on stage at GTC roughly three months ago, which in hardware terms is the equivalent of the ink still being wet. The holdup is not the silicon. It is a circuit board: a 78-layer PCB midplane that nobody can yet manufacture at the volume and yield a rack line needs. Nvidia has not confirmed the report, but the knock-on decisions SemiAnalysis describes are severe. A rack variant canceled, the top Rubin Ultra package halved, and a scaling gap that hands AMD and Google an opening they did not have last week.

What Kyber was supposed to be

Kyber is Nvidia's rack architecture for the Rubin Ultra generation, the successor to the Oberon racks that house today's NVL72 systems. The NVL144 configuration binds 144 GPUs into a single NVLink scale-up domain, one giant coherent accelerator that software treats as one machine. That "one machine" trick is the whole point of a rack-scale system: the more GPUs you can weld into a single memory-coherent domain, the larger the model you can train or serve without paying the latency tax of hopping across slower network links.

To make 144 GPUs behave like one, every accelerator has to talk to every other at full NVLink bandwidth. That traffic runs through a shared spine at the back of the rack called the midplane. And the midplane is where the wheels came off.

The bottleneck is a circuit board, not a chip

Per SemiAnalysis, Kyber's midplane is an orthogonal backplane built as a 78-layer PCB, assembled from three stacked 26-layer boards. That is an absurd amount of copper to align. Picture printing 78 transparencies, each with hair-thin traces, and having to stack every one of them in perfect registration so no signal on layer 12 crosses one on layer 60. Now do it at data-center yields, not in a lab. The silicon was ready; the parking lot it plugs into was not.

The reason the layer count exploded is bandwidth. Pushing NVLink at 448G-class SerDes rates across a passive backplane demands exotic laminates and trace widths down at the tens-of-microns scale, and every extra bit of density means more layers and tighter tolerances. Nvidia has spent a decade proving it can design the fastest chip in the room. Kyber is a reminder that a rack is a manufacturing problem, and manufacturing does not care how good your GPU is.

The dominoes: what got cut to route around it

A rack slipping a year is bad. What Nvidia reportedly did to plug the hole is the part builders should read twice.

• NVL72x2 is canceled. The obvious workaround was to bolt two existing Oberon racks back to back for a stopgap large domain. SemiAnalysis says cloud providers pushed back and the design was scrapped outright. So there is no easy bridge system to sell while Kyber cooks.
• Rubin Ultra gets halved. The planned four-chip Rubin Ultra package is out; only the two-chip variant survives, at roughly half the compute per socket. The flagship of the generation is shipping as a lighter model than the one on the slides.
• NVL576 waits on optics. The even larger 576-GPU domain, which strings eight Oberon racks together over co-packaged optics, is delayed or held to low volume, with co-packaged optics reportedly not mature until the following Feynman generation.

The opening this leaves

Here is why this is not just a supply-chain footnote. Scale-up domain size, how many accelerators you can fuse into one coherent machine, is the axis where Nvidia has led by a mile. A year without a validated next-gen midplane means that lead stops growing right when rivals are closing.

SemiAnalysis names two beneficiaries. AMD's MI500X and Google's TPUv8i "Broadfly" are both pushing hard on rack-scale interconnect, and a Kyber gap gives them a window to match or exceed Nvidia on domain size for the first time in years. Nvidia still wins on software, ecosystem, and raw per-chip throughput. But "the biggest single machine you can rent" has been a Nvidia-only sentence for a long time, and for a stretch of 2027 it may not be.

Why a builder should care

• The wall is physical now, not logical. For years the AI hardware story was transistors and TFLOPs. This delay is copper laminate, layer counts, and optics yield. The frontier is bottlenecked on things you laminate and solder, and those do not follow a training-loss curve. Plan roadmaps around manufacturing risk, not just spec sheets.
• Current-gen scarcity just got a longer lease. No stopgap NVL72x2 and a year-late Kyber means today's Blackwell and early-Rubin capacity stays in demand well into 2027. If you were betting on a 2027 price cliff as next-gen racks flooded in, push that expectation out. Renters, budget for high current-gen prices for longer.
• A second serious scale-up vendor is worth designing for. If AMD and Google genuinely close the domain-size gap, "we only target CUDA" gets riskier and portability gets cheaper insurance. Keep your inference and training stack one abstraction layer away from a single vendor's interconnect.
• Roadmap slides are marketing, not a delivery date. A part demoed on a keynote stage in the spring slipped a full year by summer. Treat vendor timelines for unreleased silicon as aspirations, and do not commit capacity plans to a rack you cannot yet buy.

Key Takeaways

• SemiAnalysis reports Nvidia's Kyber NVL144 rack has slipped more than 12 months to 2028, about three months after Jensen Huang demoed it at GTC; Nvidia has not confirmed it.
• The blocker is manufacturing, not design: a 78-layer PCB midplane (three stacked 26-layer boards) needed to carry NVLink at 448G-class rates across a passive backplane.
• Fallout includes the canceled NVL72x2 back-to-back rack, a Rubin Ultra package cut from four chips to two (roughly half the compute), and an NVL576 held up on co-packaged optics.
• The delay stalls Nvidia's lead on scale-up domain size, opening a window for AMD's MI500X and Google's TPUv8i "Broadfly."
• For builders: expect current-gen GPU scarcity and pricing to persist into 2027, treat vendor roadmap dates as aspirations, and keep your stack one layer away from a single interconnect.

Sources: CNBC, SemiAnalysis, NVIDIA Technical Blog (Vera Rubin POD)