$312M for an Inference Chip With No HBM, and Arm Is In

TL;DR

OLIX, a British chip company founded in 2024, has raised $312 million at a $3.3 billion valuation. The pitch is not another Nvidia-shaped accelerator. It is an inference part that deliberately uses none of the three things the rest of the industry is queued up for: high-bandwidth memory, advanced packaging, and a leading-edge process node. Weights sit in on-die SRAM, and data moves between chips over light instead of copper. Arm and Hudson River Trading are in the round. The chip, DX-1, reaches customers in the second half of 2027.

What OLIX is actually building

The announcement describes a rack-scale platform called X-1 rather than a single accelerator. A model gets distributed across many chips, with each chip specialized for one stage of token production instead of every chip trying to do everything adequately. OLIX's framing is a datacenter as a production line, not a warehouse of identical general-purpose workers.

DX-1 is the first part off that line, and it targets decode specifically. OLIX claims over 10,000 output tokens per second per user on a 100 billion parameter model, higher output token throughput per watt than general-purpose chips, and an architecture that scales to models of 10 trillion parameters and above.

Picking decode as the target is a defensible read of where inference actually hurts. Prefill chews through the whole prompt in parallel and looks like a matrix multiply, which silicon is already good at. Decode produces one token, then the next, then the next, dragging weights and KV state across the memory bus every single time. That is the stage where interactivity goes to die, and it is bandwidth-bound in a way that more FLOPs do not fix.

The interesting part is the bill of materials

Strip away the funding number and the story is a list of things OLIX says DX-1 does not need. No HBM. No advanced packaging. No leading-edge silicon node. Its investor Plural made the same point back in February: the design sidesteps all three, which are precisely the parts of the supply chain where you wait in line behind hyperscalers with better purchase orders than yours.

The replacement for HBM is SRAM, sitting on the die itself. Think of HBM as a warehouse next door: enormous, and every token means another trip out to the loading dock. SRAM is the parts tray on your bench, so you never walk anywhere, but the tray is small. OLIX's answer to the small tray is a lot of benches wired together with light rather than a longer walk.

That is what the optical interconnect is for. Reporting on the round describes it as a "slow and wide" design that moves data between chips as light instead of over copper traces, claiming lower latency and lower energy per bit. The name will not win a marketing award, but wide-and-unhurried is exactly the shape you want when the bottleneck is bytes moved per token, not clock speed.

Optical, but not analogue

Worth separating this from the photonic-computing pitch you may have already rolled your eyes at. Plural describes the part as an optical digital processor doing bit-perfect computation, not analogue approximation. Light is being used to move data, not to do fuzzy matrix math with interference patterns and a prayer. When the February round landed, the same architecture was described as an Optical Tensor Processing Unit with the interconnect optical and the memory on-chip SRAM.

Who wrote the checks

New money came from Fundomo, Arm, and Hudson River Trading, with Netflix co-founder Reed Hastings in as an angel. Existing backers Hummingbird Ventures, Plural, Crane, Creandum, Phoenix Court, and Transition all increased their commitments.

Arm is the name to sit with. A company whose entire business is licensing the architecture other people build on does not casually take a position in a startup proposing a different shape of inference compute. Read it as a hedge, a listening post, or a bet, but it is not a rounding error on anyone's strategy.

The round also came with governance signals: Professor Nick McKeown joins the board, a co-inventor of software-defined networking, OpenFlow and P4, Professor Emeritus at Stanford and the 2025 Marconi Prize winner. Matt Briers, CFO at Wise for nine years, takes the same seat here. Hiring is open across London, Bristol, Austin, Toronto and San Francisco for silicon, compiler, photonics and systems roles.

The gap between the money and the silicon

In February, OLIX raised $220 million at a valuation above $1 billion, per Verdict's writeup and SiliconANGLE's coverage at the time. Six months later the valuation is $3.3 billion. First customer access to DX-1 is targeted for the second half of 2027.

So: a Marconi laureate on the board, a CFO from Wise, $532 million raised across two rounds, and a $3.3 billion price tag. What OLIX does not have yet is a chip anyone outside the building has benchmarked.

What to hold back until 2027

• Every performance number here is a vendor claim. Ten thousand tokens per second per user, throughput per watt, scaling to 10T parameters: none of it has been independently measured, because there is nothing yet to measure.
• The SRAM math is the whole bet. On-die SRAM is fast and expensive per bit. Holding a 100B parameter working set, let alone something ten trillion wide, means an awful lot of die spread across an awful lot of chips, and the optical fabric has to make that partitioning nearly free. If it does not, "no HBM" turns into "not enough memory."
• Skipping advanced packaging cuts both ways. It genuinely removes a queue. It also removes the density advantage everyone else pays that queue for.
• Optical interconnect startups have a long history of impressive demos and slipped schedules. H2 2027 is a target, not a shipping date.

None of that makes this uninteresting. HBM supply and packaging capacity are the reasons inference costs what it costs, and a credible architecture that needs neither is worth watching even at pre-product odds. Just do not put it in a capacity plan yet.

Key Takeaways

• OLIX raised $312 million at a $3.3 billion valuation on August 3, 2026, up from $220 million at over $1 billion in February.
• DX-1 is a decode-specialized accelerator claiming over 10,000 output tokens per second per user on a 100B parameter model.
• The architecture uses on-die SRAM and an optical "slow and wide" interconnect instead of HBM, advanced packaging, or leading-edge silicon.
• The optics move data, they do not do the math: OLIX describes bit-perfect digital compute, not analogue photonic approximation.
• Arm, Hudson River Trading and Reed Hastings are new investors; Nick McKeown joins the board and ex-Wise CFO Matt Briers becomes CFO.
• No silicon reaches customers until the second half of 2027, and no third party has benchmarked any of the claims.

Sources: OLIX Series B announcement, OLIX, Verdict, Yahoo Finance, SiliconANGLE, Plural