AMD Just Bought a 17,000 Token/Sec Chip. It Runs One Model.

TL;DR

On August 6, AMD announced a definitive agreement to acquire Taalas, a Toronto startup founded in 2023 that builds what it calls Hardcore Models: chips with a specific model's weights physically etched into the mask layers, no HBM involved. Terms were not disclosed. Taalas' first test chip, the HC1, ran Llama 3.1 8B at around 17,000 tokens per second per user on an 815 mm2, 53-billion-transistor die. The catch is in the name: that chip runs Llama 3.1 8B, and it will run Llama 3.1 8B until it is thrown away.

What Taalas actually built

Every inference accelerator you have used solves the same problem: the weights live in memory, the math lives in the cores, and the bus between them is the bottleneck. HBM stacks, wafer-scale SRAM, and Groq's LPU are all different answers to "how do we get weights to the ALUs faster."

Taalas' answer is to stop moving weights at all. The HC1 stores the model in a mask-ROM recall fabric, meaning the parameter values are expressed as physical transistor connections laid down at fabrication. A second SRAM recall fabric on the same die holds the parts that have to change at runtime: the KV cache and fine-tuning adapters. The Register describes the split; the die itself is 815 mm2 on TSMC's 6nm node with 53 billion transistors, per ServeTheHome.

The useful analogy: a GPU is a photocopier that will reproduce any page you feed it, while the HC1 is a printing press with the plates already cut. The press is absurdly faster and cheaper per page, right up to the moment you want to print a different book.

The numbers, and the asterisk

When Taalas unveiled the HC1 in February 2026, it claimed 16,960 tokens per second on Llama 3.1 8B, which it framed as 48x faster than Nvidia GPUs and 8.5x faster than Cerebras accelerators at the time. CNX Software logged a peak of about 17,000 tokens/s, with 15,000 to 16,000 on typical queries, and Taalas' own comparison against Cerebras also claimed 20x lower build cost and 10x lower power.

Now the asterisk, and it is a large one. That throughput comes from a custom 3-bit base data type with a mix of 3-bit and 6-bit parameters, chosen specifically so all 8 billion weights fit on one die. Unite.AI notes the quantization is aggressive enough to visibly degrade output quality relative to the GPU benchmarks it is being compared against. HC2, the second-generation part, moves to standard 4-bit floating point and targets roughly 20 billion parameters, which implies about 50 accelerators to hold a trillion-parameter model.

So the honest reading of the headline number is not "48x faster than a GPU." It is "48x faster than a GPU at running a smaller, blurrier version of a model from July 2024." Which is still a genuinely interesting thing to be.

Why the fab step is the actual product

The reason this is not simply a very fast ASIC is the manufacturing path. Because only the final metal layers encode the weights, a new model or a new version of an existing model requires changing two mask layers rather than a full tape-out. Unite.AI reports TSMC turnaround of roughly two months for a customized part, against roughly six months for a processor like Nvidia's Blackwell, and says even a previously unseen model fits inside that two-month window.

Whether that loop holds at volume is the open question. Reticle limits mean anything much past 20B parameters needs partitioning across multiple chips, which drags in multi-die packaging and test complexity that a single 815 mm2 part conveniently avoids.

Why AMD, and why now

AMD's press release is the usual roadmap language. Vamsi Boppana, Senior Vice President of AMD's Artificial Intelligence Group, said Taalas' technology and team "strengthen our AI portfolio by delivering differentiated inference performance and efficiency," and the company positions Taalas alongside Helios rackscale systems, Instinct GPUs, EPYC CPUs, and ROCm. The deal is subject to customary closing conditions and regulatory approvals, and The Register puts the expected close in Q4 2026.

The strategic read is sharper than the release. In December 2025 Nvidia paid roughly $20 billion to license Groq's LPU inference architecture and absorb its leadership, a deal that drew a Senate investigation and an ongoing argument about whether a licensing agreement that takes the founders too is really a licensing agreement. AMD's counter-move is smaller, cleaner, and structurally an actual acquisition.

It also lands two weeks after AMD's joint inference product with Cerebras, which splits a single request so Helios racks handle prefill and Cerebras wafers handle decode. Taalas fits the same disaggregated shape, with GPUs doing prompt processing and model-specific silicon doing token generation, except AMD would own both halves. If you were Andrew Feldman, you might read the last two weeks with some interest.

The obsolescence problem nobody has solved

The obvious objection: baking a model into silicon is speed-running obsolescence. Llama 3.1 8B shipped in July 2024. In model years the HC1 arrived as an antique with a very fast heartbeat.

The counterargument is that "frontier" and "useful" have been diverging for a while. A large share of production inference is not agentic reasoning; it is classification, extraction, routing, moderation, and summarization at volume, where a competent 8B to 20B model at 10x to 100x lower cost per token beats a frontier model you cannot afford to call on every row. Autonomous systems want predictable latency more than they want this month's benchmark leader.

That is a real market. It is also a smaller and less glamorous market than the slide deck implies, and it only works if model architectures stop churning long enough for a two-month fab loop to be economically sane.

What this means if you build things

• Nothing changes this quarter. The deal has not closed, HC2 is not shipping to customers, and there is no public roadmap for a Taalas part you can rent.
• Watch which models get etched. The moment a vendor commits a specific open-weight checkpoint to mask layers, that checkpoint gets a multi-year cost advantage that has nothing to do with its benchmark scores. Model choice starts being partly a hardware decision.
• Quantization stops being your problem and starts being the silicon's. If the chip only exists in 3-bit or 4-bit form, your eval suite needs to test the quantized weights, not the reference ones.
• Disaggregation is now the default architecture. Prefill and decode have genuinely different hardware appetites, and three separate companies have now shipped or bought silicon that assumes you will split them.

Key Takeaways

• AMD signed a definitive agreement on August 6, 2026 to acquire Taalas, a 2023-founded Toronto startup building model-specific inference silicon. Terms were not disclosed; close is expected in Q4 2026 pending regulatory approval.
• Taalas etches model weights into mask-ROM on the die, with a separate on-chip SRAM fabric for KV cache and fine-tuning adapters. No HBM holds the weights.
• The HC1 test chip is 815 mm2 on TSMC 6nm with 53 billion transistors, and served Llama 3.1 8B at about 17,000 tokens/s per user, using a custom 3-bit and 6-bit mixed data type that measurably degrades quality.
• Taalas claimed 48x Nvidia GPUs and 8.5x Cerebras on speed, plus 20x lower build cost and 10x lower power against Cerebras. All are vendor figures against vendor-chosen baselines.
• Founders Ljubisa Bajic, Lejla Bajic, and Drago Ignjatovic are ex-AMD and ex-Tenstorrent; the company raised about $219 million total, and built the first chip with 24 engineers on roughly $30 million.
• This is AMD's answer to Nvidia's roughly $20 billion Groq licensing deal, and it makes AMD an owner rather than a partner in the decode half of disaggregated inference.

Sources: AMD investor relations press release, The Register, ServeTheHome, BetaKit, Unite.AI, CNX Software, Taalas